Verification of Fault Tolerance by Means of Fault Injection into VHDL Simulation Models*

This paper describes and illustrates the application of a strategy for testing fault tolerance by means of fault injection. The proposed approach encompasses a method for modelling fault tolerance together with a strategy for testing several classes of fault tolerance mechanisms. The modelling approach distinguishes two main abstraction levels: (i) a data flow diagram of the general organisation of the fault tolerance and of the interactions between the fault tolerance mechanisms, (ii) behavioural models of the individual mechanisms. The behavioural models allow for structural or functional testing criteria to be identified. They are used for determining the activities to be applied and the faults to be injected in order to cover the selected criteria. The target fault-tolerant system considered for exemplifying our approach features several fault tolerance mechanisms (self-checking, voting, clock synchronization, etc.) and is implemented as a VHDL model. It is built on a versatile environment allowing the analysis of fault-tolerant real-time distributed architectures. The MEFISTO tool has been extended to support the proposed fault injection scheme.